More than a standalone IP block, Wupatec’s DPD solution is designed to help RF and telecom engineers improve power amplifier linearity while maintaining high output power and efficiency.
Built for demanding digital front-end architectures, the DPD IP Core combines a hardware correction core, signal capture capabilities, and software-driven control to support advanced RF transmitter development.
DPD IP Core
Digital Pre-Distortion for RF Power Amplifier Linearization
The DPD IP Core is designed to compensate for the nonlinear behavior of RF Power Amplifiers in transmitter systems. By applying digital correction before the analog conversion stage, it helps engineers improve Power Amplifier efficiency, maximize output power, and maintain compliant signal distortion levels.
The solution combines a hardware correction core, signal capture, and software-driven control for correction parameter computation and system optimization.
KEY FEATURES
FDD & TDD Support
Supports Frequency Division Duplex and Time Division Duplex operation with automatic timeslot detection.
Scalable Hardware Core
Customizable implementation for performance, latency, capture depth, and available DSP/RAM resources.
Signal Capture
Includes signal capture and analysis capabilities to support correction parameter computation and transmitter performance optimization.
Runtime Configuration
DPD model complexity can be configured at runtime to balance linearization performance and update speed.
FPGA & RFSoC Compatibility
Supports AMD Zynq UltraScale+ RFSoC, Zynq UltraScale+, UltraScale/UltraScale+ FPGAs, Zynq 7000 and 7-Series FPGAs.
Software
C API with support for Linux or Bare-metal running on Zynq PS or MicroBlaze soft core processor
Contact us
+33 05 55 42 62 44
Head Office: 20 rue Atlantis, 87068, Limoges, France